1. Technical Field
Various embodiments generally relate generally to a semiconductor memory device and a method of operating the same and, more particularly, to a semiconductor memory device having a three-dimensional structure and a method of operating the same.
2. Related Art
Among semiconductor memory devices, a NAND flash memory device is a typical non-volatile memory device. A memory array of a NAND flash memory device includes a plurality of memory blocks. Each of the memory blocks includes a plurality of memory cell strings. Each of the memory cell strings is coupled between a bit line and a common source line. More specifically, each of the memory strings includes a plurality of memory cells that are coupled in series between a drain selection transistor and a source selection transistor. The drain selection transistor may have a drain coupled to the bit line, and the source selection transistor may have a source coupled to the common source line.
In general, a memory cell string is two-dimensionally formed on a substrate. In order to increase the degree of integration, a cell size is to be reduced. However, two-dimensional memory strings are reaching physical limits in reducing the cell size. Accordingly, three-dimensional non-volatile memory strings have been proposed.
A memory cell string may include a vertical channel layer that is formed in a vertical direction to a semiconductor substrate, a memory layer that includes a charge storage layer and an insulating layer formed on a surface of the vertical channel layer, a conductive layer configured as a word line and a conductive layer configured as a selection line (drain selection line or source selection line) that are penetrated by the vertical channel layer, and an insulating layer that is formed between the conductive layer configured as the word line and the conductive layer configured as the selection line.
FIG. 1 is a circuit diagram of a memory cell string of a semiconductor device having a pipe-shaped bit cost scalable (PBiCS) structure.
Referring to FIG. 1, a memory cell string of a semiconductor memory device may include first group memory cells C1 to C4 and second group memory cells C5 to C8. The first group memory cells C1 to C4 may be coupled in series between a source selection transistor SST, coupled to a source line SL, and a pipe transistor PTr. The second group memory cells C5 to C8 may be coupled in series between a drain selection transistor DST, coupled to a bit line BL, and the pipe transistor PTr.
The pipe transistor PTr may electrically connect a channel region of the first group memory cells C1 to C4 to a channel region of the second group memory cells C5 to C8 in response to a string selection signal String.
FIG. 1 also illustrates drain selection line DSL, source selection line SSL and word lines WL1-WL8.